The phase-locked loop (PLL) is a versatile electronic circuit used in a wide variety of applications, including frequency synthesis, clock recovery, clock multiplication, and clock regeneration. In large, high-speed integrated circuits (including application-specific integrated circuits, field-programmable gate arrays, network processors, and general purpose microprocessors), PLLs have become commonplace. On-chip phase-locked loop clock multipliers are used on these chips to generate a high-frequency clock signal that is a multiple of, and in phase with, a system clock or I/O clock. PLLs may also be used on these chips to resynchronize and realign clocks in deep clock distribution trees to reduce clock skew.
PLLs utilize a phase frequency detector (PFD) to compare a reference clock to a clock generated by a voltage controlled oscillator (VCO) and feed back to the PFD. Reference clock feedthrough degrades high frequency phase noise performance of PLLs so that they achieve worse short term clock jitter. PLLs may implement sample-reset techniques to improve the reference clock feedthrough performance.